DDR2/DDR3 memory controller calibration IP for ASICs and FPGAs

This is an interesting one… The challenge of memory controller design is timing closure. With chips implemented at 40nm and below, the normal approach requires implementation of multiple clock delay lines within the PHY, then testing the first hundred engineering samples to permanently set the clock read delay for the optimal yield.

The folks at Semi IP innovator Uniquify (www.uniquify.com) say that they’ve invented "Self-Calibrating Logic (SCL)," whereby the memory controller does a self-test on EVERY power up to select the optimal delay. In the case of ASIC / ASSP / SoC designs, the result is higher yield, even if the foundry process drifts.

The reason this was interesting to me is that the original release (show below) is focused on ASIC / ASSP / SoC design. However, although it doesn’t explicitly say so, the release sort of implies some digital IP block that fine-tunes the analog PHY parameters. So I thought to myself: “If this is the case, then it should be possible to implement the IP block in the FPGA programmable fabric and use it to fine-tune the analog PHY.” This might require some tight collaboration with the FPGA vendor, but that shouldn’t be a problem if this is to their end-users’ advantage.

So I pinged the folks at Uniquify posing this question, and they replied: “You are CORRECT. (I can never hear that often enough … and I live in hopes that one day it will be my wife who says it [grin].) The SCL technology and patent cover a basic technique that is applicable to FPGA as well as ASIC or full custom ICs. So ultimately – YES – this is an FPGA story as well.”

OK, keeping this in mind, the original release is as follows:

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Uniquify, a Silicon Valley semiconductor IP start-up (www.Uniquify.com), today announced that it has been granted a United States patent covering its innovative solution for designing DDR (double data rate) memory controllers that satisfy challenging timing requirements. The company’s patented ‘Self-Calibrating Logic’ (SCL) permits SoC (system-on-chip) designs that use Uniquify’s memory controller IP (intellectual property) to automatically fine-tune critical timing parameters after the SoCs are installed in system boards.

Today’s deep sub-micron SoC designs integrate DDR memory controllers that operate at multi-GHz clock rates. At these clock rates, system-level memory read-write timing margins are measured in picoseconds. Designing DDR PHYs that satisfy these timing requirements can require exhaustive rounds of incremental IC design modifications, and the resulting silicon often fails to produce high yielding devices in high-volume production.

Uniquify’s memory controller IP, which incorporates its patented SCL technology, performs a system self-test on power-up that allows the controller’s PHY circuitry to automatically fine-tune timing parameters every time the host SoC is reset. Not only does SCL eliminate the need for excessive design tweaks to achieve timing closure during the SoC development stage, chips with SCL are much higher yielding due to their ability to automatically adapt their timing characteristics for a wide range of system-level design choices and for variations in the SoC foundry process.

“System level timing requirements are the most challenging part of memory controller design. Precise details about the system board design, the type of external memory devices used, and even details about the host SoC may not be finalized--or may not be well characterized--when the DDR PHY is initially designed,” explained Uniquify CEO and founder Josh Lee. “Our patented SCL technology allows Uniquify to move the final determination of exact timing parameters from the IC design stage to system power-on in the field, when all of the characteristics that affect timing are finalized and implemented.”

Conventional approach too rigid
The conventional approach to managing critical timing requirements is for chip designers to measure the actual timing characteristics on the first several hundred SoC engineering samples, and then manually set timing parameters using programmable on-chip registers. Permanently setting timing parameters after only a few hundred samples have been fabbed, however, has proven problematic for deep sub-micron designs.

“At current process nodes even minor variations in the foundry process can cause timing parameters to drift, which will produce significant yield loss in volume production,” said Uniquify DDR Solutions Architect Mahesh Gopalan. “SCL automatically accommodates normal process variation--without yield loss--by continuously modifying timing parameters at every power-up. Even system-level aging, which can alter board-level trace delays over years of use, can be accommodated by SCL, thereby improving overall system reliability.”

Patented technology already widely used
Uniquify uses SCL technology in the PHY part of its memory controller IP. The company’s DDR1, DDR2, DDR3 and DDR2/3 Combo IPs have been licensed to companies worldwide.  For more information, please visit www.Uniquify.com.